Keynote Speakers

Dr. Vijay Krishnan Narayan

Department of Computer Science and Engineering

Pennsylvania State University

354D Information Sciences and Technology Building

University Park, PA 16802

Title : ThirdEye: Visual Assist for Grocery Shopping

Tentative Date: 18th Dec 2017

Tentative Time: TBA

Title : ThirdEye : Visual Assist for Grocery Shopping

Abstract : Shopping is widely considered as a relaxing leisure activity. However, grocery shopping can be a frustrating experience for those with visual impairment. While getting to a grocery shop itself is not as much of a challenge for them, locating and picking the items in the grocery shelf becomes a task as challenging as picking a needle from the haystack. Imagine picking up five items for your dinner recipe from a typical grocery store in the US that carries around 35,000 unique items and can have more than 30 aisles spanning 45,000 square meters. This talk will showcase synergistic advances in algorithms, architectures and interface design for assisting those with visual impairment to do shopping.

Biography : Vijay Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is the director of the NSF Expeditions-in-Computing Program on Visual Cortex on Silicon and a thrust leader for the DARPA-MARCO LEAST Center. He has published more than 400 papers and won several awards in recognition of his research in power-aware systems, embedded systems and computer architecture. He is a fellow of IEEE and ACM.

Title : Challenges of Converging Nanoelectronics and Nanotechnology for Internet of Things

Abstract : Current trends in Internet of Things (IoT) require the convergence of Nanoelectronics, Nanotechnology, Communication Technology and Information Technology. Sensor systems monitoring environment, health care, water quality, vehicle traffic, smart cities are becoming the norm. Despite extended range of applications low power requirement is the key to these nanosystems. Incorporation of different nanodevices into these nanosystems with functionalities that do not necessarily scale according to “Moore’s Law,” but provide additional value in different ways (more than Moore), is necessary. It is therefore important to get exposed to the current trend in chip fabrication, device structures and fabrication (gate stack design and fabrication), device and circuit relationship and design, reliability of new devices and processes. Furthermore, nanoelectronic devices with extremely low power consumption depends on the next generation high-k deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent annealing temperatures. In this talk, some of the recent developments in device fabrication for electronics devices and IoT devices will be outlined.

Dr. Durgamadhab (Durga) Mishra

Professor & Associate Chair for Graduate Program, FELLOW of The Electrochemical Society

Department of Electrical and Computer Engineering, New Jersey Institute of Technology Newark, NJ, USA

Title : Challenges of Converging Nanoelectronics and Nanotechnology for Internet of Things

Tentative Date: 18th Dec 2017

Tentative Time: TBA

Biography : Durga Misra is a Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, USA. He served as the Director of Microelectronics Research Center at NJIT andhad a short-term appointment at Bell Laboratories, Murray Hill, NJ, in 1997. His current research interests are in the areas of nanoelectronic/optoelectronic devices and circuits; especially in the area of nanometer CMOS gate stacks and device reliability. He is currently a Distinguished Lecturer of IEEE Electron Devices Society (EDS) and serving in the IEE EDS Board of Governors. He is a Fellow of the Electrochemical Society (ECS) and served in the ECS Board as a Board Member (2008-10). He received the Thomas Collinan Award from the Dielectric Science & Technology Division and Electronic and Photonic Division Award from ECS. He edited and co-edited more than 40 books and conference proceedings in his field of research. He has published more than 95 technical articles in peer reviewed Journals and more than 160 articles in International Conference proceedings including 75 Invited Talks. He has graduated 15 PhD students and 35 MS students. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in

Title : Considerations for Designing Secure and Efficient Nanoelectronic Computer Architectures

Abstract : In the integrated circuits industry today, electronic devices are being scaled to the point where feature sizes are on the order of tens or even a few nanometers such that defect rates are increased, leakage is non-negligible and quantum effects have begun to dominate. With so many potential issues facing conventional microelectronic technologies, novel approaches to circuit design and even non-classical devices warrant exploration. Add to this mix of challenges the reality of security vulnerabilities that must be addressed at early design stages such that emerging nanoelectronic systems must be both efficient and trustworthy. As a specific case study, this talk will focus on memristor based systems. Given their low power operation and small footprint, memristors have emerged as excellent candidates for future memory and logic. However, the non-volatility of memristors also presents certain security challenges whereby sensitive data may be vulnerable. At the same time, memristors also show promise for effective security primitives such as physical unclonable functions and random number generators.

Dr. Garrett S. Rose

Associate Professor, Department of Electrical Engineering and Computer Science,

The University of Tennessee, Knoxville, TN 37996-2250 USA

Title : Considerations for Designing Secure and Efficient Nanoelectronic Computer Architectures

Tentative Date: 19th Dec 2017

Tentative Time: TBA

In this talk we will consider the security pros and cons of nanoelectronic systems and also discuss design techniques that best balance security concerns with performance needs. In addition to addressing energy-efficiency and security in conventional systems, nanoelectronic technology should also be considered as a means of enabling truly novel forms of computer architectures. To this end, nano-enabled neuromorphic systems offer exciting opportunities for future computing applications. Again, as such novel technologies and novel approaches to computing continue to emerge, careful attention must be paid to balanging security issues against traditional energy performance metrics.

Short Biography : Garrett S. Rose received the B.S. degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. His Ph.D. dissertation was on the topic of circuit design methodologies for molecular electronic circuits and computing architectures.

Presently, he is an Associate Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville where his work is focused on research in the areas of nanoelectronic circuit design, neuromorphic computing and hardware security. Prior to that, from June 2011 to July 2014, he was with the Air Force Research Laboratory, Information Directorate, Rome, NY. From August 2006 to May 2011, he was an Assistant Professor in the Department of Electrical and Computer Engineering at the Polytechnic Institute of New York University, Brooklyn, NY. From May 2004 to August 2005 he was with the MITRE Corporation, McLean, VA, involved in the design and simulation of nanoscale circuits and systems. His research interests include low-power circuits, system-on-chip design, trusted hardware, and developing VLSI design methodologies for novel nanoelectronic technologies.

Dr. Rose is a member of the Association of Computing Machinery, IEEE Circuits and Systems Society and IEEE Computer Society. He serves and has served on Technical Program Committees for several IEEE conferences (including ISVLSI, GLSVLSI, NANOARCH) and workshops in the area of VLSI design. In 2010, he was a guest editor for a special issue of the ACM Journal of Emerging Technologies in Computing Systems that presented key papers from the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’09). From April 2014 through March 2017 he was an associate editor for IEEE Transactions on Nanotechnology.

Title : QUADSEAL : A Hardware Countermeasure against Side channel Attacks on AES

Abstract : Deep devastation is felt when privacy is breached, personal information is lost, or property is stolen. Now imagine when all of this happens at once, and the victim is unaware of its occurrence until much later. This is the reality, as increasing amount of electronic devices are used as keys, wallets and files. Security attacks targeting embedded systems illegally gain access to information or destroy information. Advanced Encryption Standard (AES) is used to protect many of these embedded systems. While mathematically shown to be quite secure, it is now well known that AES circuits and software implementations are vulnerable to side channel attacks. Side-channel attacks are performed by observing properties of the system (such as power consumption, electromagnetic emission, etc.) while the system performs cryptographic operations. In this talk, differing power based attacks are described, and various countermeasures are explained. In particular, a countermeasure titled Algorithmic Balancing is described in detail. Implementation of this countermeasure in hardware and software is described. Since process variation impairs countermeasures, we show how this countermeasure can be made to overcome process variations.

Dr. Sri Parameswaran

Professor & Program Director for Computer Engineering, School of Computer Science and Engineering

The University of New South Wales, Australia

Title : QUADSEAL : A Hardware Countermeasure against Side channel Attacks on AES

Tentative Date: 19th Dec 2017

Tentative Time: TBA

Short Biography : Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He also serves as the Postgraduate Research and Scholarships coordinator at the same school. Prof. Parameswaran received his B. Eng. Degree from Monash University and his Ph.D. from the University of Queensland in Australia. He has held visiting appointments at University of California, Kyushu University and Australian National University. He has also worked as a consultant to the NEC Research laboratories at Princeton, USA and to the Asian Development Bank in Philippines. His research interests are in System Level Synthesis, Low power systems, High Level Systems, Network on Chips and Secure and Reliable Processor Architectures. He is the Editor-in-Chief of IEEE Embedded systems Letters. He serves or has served on the editorial boards of IEEE Transactions on Computer Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems and the Design Automation of Embedded Systems. He has served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

Dr. Ashok Srivastava

Wilbur D. and Camille V. Fugler, Jr., Professor of Engineering, Professor of Electrical & Computer Engineering,
School of Electrical Engineering & Computer Science, Louisiana State University, Baton Rouge, LA 70803

Title: Reduced Dimension-based Emerging Novel Switching Transistors and Interconnects for Post-CMOS Electronics

Tentative Date: 20th Dec 2017

Tentative Time: TBA

Title : Reduced Dimension-based Emerging Novel Switching Transistors and Interconnects for Post-CMOS Electronics

Abstract : Focus of this presentation will be on reduced dimension materials such as carbon nanotubes, graphene and other than graphene-based emerging novel switching transistors and interconnects for future integrated circuit design and wide-ranging other applications. Addressing the needs of post-CMOS electronics, development of current transport models of transistors based on these materials will be presented which can be used for the design of ultra-low power and high frequency nanoscale integrated electronic circuits. Use of carbon nanotubes, graphene and graphene-copper hybrid material as a possible solution for the replacement of copper interconnect in nanometer CMOS technology nodes will also be included in presentation.

Biography : Dr. Ashok Srivastava obtained M. Tech. and Ph.D. degrees in Solid State Physics and Semiconductor Electronics area from Indian Institute of Technology, Delhi in 1970 and 1975, respectively. He joined the Department of Electrical & Computer Engineering of Louisiana State University, Baton Rouge in 1990 and is Wilbur D. and Camille V. Fugler, Jr., Professor of Engineering in the School of Electrical Engineering & Computer Science. In year 2011, he held visiting appointments at the Institute of Electrical Engineering NanoLab, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland; Katholiek Universiteit/Inter-university Microelectronics Center (IMEC), Leuven, Belgium; Indian Institute of Information Technology (IIIT), Allahabad; and in year 2001 at the Philips Research Laboratory, Eindhoven, The Netherlands. His other past appointments include Central Electronics Engineering Research Institute, Pilani, India (1975-84); Birla Institute of Technology and Science, Pilani, India (1975); North Carolina State University, Raleigh (1985-86); State University of New York, New Paltz (1986-90); University of Cincinnati, Cincinnati (1979); University of Arizona, Tucson (1979-80); Kirtland Air Force Base, New Mexico (Summer 1996); and Jet Propulsion Laboratory/California Institute of Technology, Pasadena (Summer 2004).

Dr. Aviral Shrivastava

Associate professor, School of Computing, informatics, and Decision Systems Engineering, School of Electrical, Computer and Energy Engineering, Arizona State University, USA.

Title: Time in Cyber-Physical Systems

Tentative Date: 20th Dec 2017

Tentative Time: TBA

Title : Time in Cyber-Physical Systems

Abstract : Cyber-Physical systems are those that tightly integrate physical and computational systems. One of the big challenges in distributed cyber-physical systems is establishing a common notion of time between the physical world and the computational system. Many modern CPS, especially industrial automation systems, require the actions of different computational systems to be synchronized at much higher rates than is possible through ad hoc designs. Fundamental research is needed in synchronizing clocks of computing systems to a higher degree, and even if the clocks are synchronized, designing CPS nodes so that they can perform actions in a synchronized manner is challenging. We need to find ways to specify distributed CPS applications, ways to specify and verify timing requirements on distributed CPS, confident top-down design methodologies that can ensure the system meets its timing requirements in the first go, dynamically creating and dissolving timing domains using differently build components, and much more.

In this talk, I will present some of the work that we have done, and some of the ideas that we want to pursue in order to solve the challenge of confident and simplified CPS design (from the timing perspective). We believe that confident CPS design is possible only when the timing requirements of CPS are specified in the application itself, and not as a separate document. It should not be a list of separate requirements, but must be married to the application specification in as natural way as possible. Second, we need techniques to design the CPS in one-shot. Provably correct by construction is very good, but even design methodologies that improve the confidence in design are also very important. Finally, there should be automated methods to test the CPS.

Biography : Prof. Aviral Shrivastava is Associate Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML) ( He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award Recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. His 2 students have received the outstanding MS thesis award in CSE at ASU. His papers have been the best paper candidate at DAC 2017, ASPDAC 2008, and won the best student paper award at VLSI 2016. His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, predictability, performance, temperature, energy, reliability and robustness. NSF and several industries including Microsoft, Raytheon Missile Systems, Intel, Nvidia, etc fund his research. He serves on organizing and program committees of several premier embedded system conferences, including DAC, ICCAD, ISLPED, CODES+ISSS, EMSOFT, CASES and LCTES, and regularly serves on NSF and DOE review panels.