Session 18

Session 18 (Special) : Gated Clock Distribution for Silicon chips

Date : 20-12-2017 Time : 11:00 – 12:00

  1. Alak Majumder, Pritam Bhattacharjee. “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”
  2. Bipasha Nath, Alak Majumder. “Binary Counter Based Gated Clock Tree for Integrated CPU Chip”